1. Field of the Invention
The present invention generally relates to semiconductor storage structures and, more particularly, to dynamic random access memories of extremely high storage capacity fabricated on chips of limited size.
2. Description of the Prior Art
It is generally recognized that increased integration density in integrated circuits (ICs) provides benefits in both improved performance and manufacturing economy. Increased proximity of devices formed on a chip reduces connection length and capacitance; reducing signal propagation time and increasing noise immunity. Increased noise immunity may, in turn, allow reduction in operating voltages which allows further scaling of devices to smaller sizes on the chip. Increased integration density also allows more devices to be formed on a chip of given size using common wafer processing steps, allowing more chips to be formed with improved uniformity without significant increase of cost. To obtain these benefits, technology has developed at a pace to double integration density about every two years in all types of ICs.
Digital storage devices must generally be used with digital data processors to provide a program of control signals for the processor and data which is to be processed in accordance with the control signals. Increased processing power of processors has also increased the amount of data which the processor may need to rapidly access. At the present state of the art, sixty-four Megabits of storage can be provided on a single chip with acceptable manufacturing yield and these chips, providing many Megabits of storage, are available at relatively low cost on the commercial market.
Increased integration density of memory chips is generally achieved by a combination of improvements in lithography which allow exposure of a resist with sufficient resolution to support smaller minimum feature size regimes and improvements in design; resulting in memory cells which require a smaller number of lithographic squares (an area corresponding to the minimum feature size) in its "footprint". At the current state of the art, feature size regimes of 0.25 micron are reliably producible and the number of lithographic squares required for a binary memory cell is eight.
However, to advance from sixteen Megabit memory chips to the currently available sixty-four Megabit memory chips, little design development was available at the cell level and the increase in capacity was principally developed through reduced feature size regimes and increased chip area. Consequently, some loss in manufacturing economy was encountered in the sixty-four Megabit generation of memory chips due principally to increased overhead of exposure systems capable of higher resolution and reduced number of chips per wafer. Lesser performance gain was achieved than between previous generations of memory chips. While minimum feature size regimes of 0.1 micron and smaller are technically feasible at the present time and foreseeable for commercial production, to develop a further generation of memory chips having a capacity of 256 Megabits per chip or greater without a major improvement in memory cell design would clearly require an unacceptable chip size and economic cost while not fully realizing potential or particularly significant performance improvement.
Accordingly, to provide an improvement in cell design suitable for a further generation of 256 Megabit or greater capacity memory chips, it is generally considered to be necessary to provide a memory cell design that can be fabricated in four lithographic squares. However, to date, no such designs have been developed.
An approach to reducing the number of lithographic squares required for a memory cell below eight, at least functionally, has involved seeking to store different, quantized, voltage levels in a cell. A memory which is operated in such a manner is thus referred to as a multi-level store. In theory, if four states (characterized by different discrete or quantized stored voltage levels) corresponding to the possible combinations of two bits, for example, can be stored in and retrieved from a memory cell having a footprint of eight lithographic squares, only four lithographic squares are effectively required per bit. When such a four-level cell is read, the (approximate) stored voltage level is quantized and decoded by sense latches to provide a digital output which corresponds to two bits. Additional levels may be provided and decoded corresponding to additional bits, depending on the ability to discriminate quantized voltage levels in the presence of noise, stored charge leakage and the like.
However, known multi-level store designs have required all quantized voltages to be supplied to a cell through a corresponding bit line, resulting in substantial drive circuit complexity and requiring substantial chip space to accommodate it (which is thus not available for storage cells). Some performance penalty is also incurred due to the necessary digital-to-analog conversion for writing and to the difficulty of level discrimination (and, possibly, error detection and recovery as the number of stored voltage levels increases). Settling time of both digital-to-analog conversion and analog level discrimination tends to increase with the number of discrete levels utilized. No alternative has been proposed which would allow avoidance of this complexity and performance penalty that would not consume substantial chip space and thus would not permit adequate increase in memory cell numbers to be realized even with a reduction of effective cell footprint or chip area per bit. Similarly, no alternative has been proposed that permits the number of power supplies used for writing the cell to be reduced below the number of bits represented or the number of voltages applied to the cell to be equal to or lower than the number of bits represented. On the contrary, in many proposed multilevel stores, the number of voltage levels which must be produced for application to the bit line may be much larger than the number of bits represented. In other words, no known or proposed cell designs have significantly relieved the tradeoff between storage density and power supply complexity and the chip space necessary to accommodate that complexity.